1. Field of the Invention
The present invention relates to a four-quadrant multiplier circuit and a squarer circuit. In particular, the invention relates to four-quadrant multiplier and squarer circuits which have an improved input range and better frequency and improved frequency response by exploiting the squarer-law characteristics of MOS transistors biased in the saturation region.
2. Description of the Prior Art
Four-quadrant multipliers are well known circuits which are often used as building blocks in larger circuit arrangements, such as adaptive filters, frequency doublers, and modulator circuits. In 1974, B. Gilbert proposed a bi-polar junction transistor (BJT) based multiplier, employing Gilbert cells. The proposal issued in an article "A High Performance Monolithic Multiplier Using Active Feedback," IEEE Journal Of Solid State Circuits, SC 9, pp. 264-377. In 1982, D. C. Soo and R. G. Meyer used the Gilbert cell concept to design a n-channel metal-oxide-semiconductor (NMOS) four-quadrant multiplier. However, Gilbert cells consume large amounts of power and provide a limited input range.
Accordingly, S. I. Liu et al. designed a complementary metal-oxide-semiconductor (CMOS) four-quadrant multiplier, using squarer-law characteristics of metal-oxide-semiconductor field effect transistors (MOSFETs) operating in their saturation region. This design was published in 1993 in the Electronics Letter, Vol. 29, pp. 1737-1738. In the same year, S. I. Liu et al. also described the design of a multiplier using the characteristics of MOSFETs in their linear region, in an article entitled "Non-Linear Circuit Applications With Current Conveyors," IEEE Proceedings-G, Vol. 140, pp. 1-6.
As discussed above, analog multipliers have been proposed which employ the characteristics of MOS devices operating in both the saturation and the linear regions. The use of MOS devices reduces power consumption, as compared to the use of bi-polar junction transistors. However, utilizing MOS transistors which are biased to operate in a linear region allows only a small input range, and provides poor frequency response. Therefore, traditional CMOS multipliers have only a narrow input range and poor frequency response, which must be improved without increasing power consumption or manufacturing costs of the multipliers.